1. Field of the Invention
The present invention relates to a mask data processor for transfer mask used in semiconductor device manufacturing.
2. Description of the Background Art
The miniaturization and high integration of large scale integrated circuits (LSIs) creates the tendency that circuit patterns formed on the LSIs have a minimum pattern dimension of 0.1 μm. A circuit pattern of an LSI can be formed by writing a design circuit on a transfer mask for implementing it on a semiconductor substrate by Laser or electron beam, and then performing a batch optical transfer of the transfer mask pattern onto the semiconductor substrate by a projection transfer apparatus.
The resolution R of the transfer apparatus is given by the following expression:R=k1λ/NA
wherein k1 is process constant, λ is waveform, and NA is numerical aperture.
The circuit pattern is formed by optical transfer method as described above, and a transfer in a defocus state produces a blurred image and thus image forming performance is deteriorated. Here, the extent of focus to which a predetermined image forming performance can be maintained is referred to as “depth of focus (DOF)” and given by the following expression:DOF=k2λ/NA2
wherein k2 is process factor.
In the present condition that the fabrication dimension is being 0.1 μm, the depth of focus to be ensured optical theoretically is being only about 0.3 μm.
On the other hand, repetitive processes such as selective etching and film formation are executed on the semiconductor substrate and irregularities (substrate irregularities) occur on the surface of the semiconductor substrate.
The occurrence of substrate irregularities was not a serious problem in such semiconductor devices that integration degree is low and substrate irregularities is smaller than the depth of focus. However, as the fabrication dimension is smaller, the substrate irregularities is recently being larger than the depth of focus, making it difficult to obtain a predetermined image forming performance.
The substrate irregularities can be eliminated by for example the following methods: one in which some dummy patterns irrelevant to a real circuit pattern are properly disposed to increase the bulk of lower portions (i.e., dummy pattern method); and the other in which a semiconductor substrate is planarized by polishing so as to cut the irregularities generated thereon by chemical mechanical polishing (CMP) method.
Meanwhile, a technique of improving planarization is disclosed in a literature, for example, Japanese Patent Application Laid-Open No. 10-247206 (the 7th to 10th columns and FIG. 1). That is, setting window frame regions obtained by dividing a mask region into a mesh, the area pattern density per window frame region is calculated and a dummy pattern is disposed in a region of high area pattern density.
A general description of the planarization technique by CMP method is disclosed in a literature, for example, “ULSI Lithography Technical Innovation,” pp 71–86, issued by Science Forum Corp.
For example, it is known that the correlation distance of a CMP process is extremely long, as much as 100 μm. Therefore, in order to perform a CMP process simulation, it is necessary to handle a layout data of full shot level about an LSI at a time. The design data of the LSI is enormous and there is for example the following problem. When this design data is unintentionally expanded to flat, its intermediate file and using memory become too large and a simulation apparatus exceeds its hardware limit, failing to execute the succeeding processing.